Verilog Interview Questions - Part 2: FSM & Race Conditions

In a Moore machine, the outputs depend only on the current state, not on the inputs directly. This makes the outputs stable for a full clock cycle but may require more states. In a Mealy machine, the outputs depend on both the current state and the inputs, which can produce output changes as soon as inputs change, often resulting in fewer states. Mealy machines can respond faster but may have glitches in the output if the input is not synchronized. Both styles are synthesizable, and the choice depends on design requirements.

A race condition occurs when the output of a simulation depends on the order of execution of concurrent statements that are scheduled in the same time slot. This happens when multiple always blocks or assignments read and write the same variable in an unpredictable order. Race conditions are avoided by using non-blocking assignments (<=) for sequential logic, using blocking assignments (=) for combinational logic inside the same always block, and not mixing both for the same variable. Proper use of the Verilog event scheduler and always blocks with well-defined sensitivity lists also helps.

A latch is inferred when a combinational always @(*) block does not assign a value to a variable in all possible paths. For example, if a case or if-else statement omits an else or default clause, the synthesis tool creates a latch to hold the previous value. To avoid latches in combinational logic, always assign every output in every branch, provide a default assignment at the top of the block, and include a default in case statements.

// Latch inferred (missing default)
always @(*) begin
  if (sel) q = a;
end

// No latch (full case)
always @(*) begin
  if (sel) q = a;
  else q = b;
end

All three are used for multi-way branching. case performs exact bit-wise comparison, including x and z values. casez treats z values (and ? in the case item) as don't-care bits. casex treats both x and z as don't-care bits. casez is commonly used for priority encoders where unused bits are masked with ?. casex should be used cautiously as it may hide X-propagation bugs during simulation.

Functions execute in zero simulation time, cannot contain timing controls (#delay, @, wait), must return a single value (or declared as void in SystemVerilog), and cannot call tasks. Tasks can consume simulation time, can have input, output, and inout ports, do not return a value, and can call both tasks and functions. Functions are more resource-efficient and are always synthesizable. Tasks can be synthesizable if they do not use timing controls.

"Full case" means all possible values of the case expression are covered, either explicitly or through a default clause. Without a full case, latches may be inferred. "Parallel case" means each case item is mutually exclusive (no overlap). If case items overlap, a priority encoder is synthesized instead of a parallel multiplexer. Synthesis tools like Synopsys support // synopsys full_case parallel_case directives, but overusing them can cause simulation-synthesis mismatches — it is better to write fully covered, non-overlapping case statements.

Synchronous reset is only applied at the active clock edge, making the design immune to glitches on the reset signal. However, it requires the reset to be present for at least one clock cycle and adds logic to the data path. Asynchronous reset takes effect immediately regardless of the clock, which is useful for ensuring a known state at power-up but can cause metastability if released near a clock edge. A common practice is to use an asynchronous reset with synchronous de-assertion (reset synchronizer) to combine the benefits of both.