Part 10 of the Tcl command reference covering Verification commands used to check and verify the design at every stage of the physical design flow. Verification commands ensure correctness of placement, clock tree, routing, timing, power, and connectivity before tape-out signoff.
The complete physical design flow follows this order:
- Design & Database Setup
- Floorplanning
- Power Planning
- Placement
- Clock Tree Synthesis
- Routing
- Optimization
- Signoff & Reports
Quick Reference: Verification Commands for EDA Tools
Verification commands are broadly categorized into check commands (fast incremental checks) and verify commands (comprehensive signoff verification). Checks are run after each major step, while verification runs are the final signoff gate before tape-out in ICC2 and Innovus.
| Command | Description |
|---|---|
check_design | Checks design for consistency and errors |
check_timing | Checks timing constraints completeness |
check_drc | Checks design rule violations |
check_power | Checks power network connectivity and integrity |
check_placement | Checks placement legality and site alignment |
check_route | Checks routing completeness and connectivity |
check_floorplan | Checks floorplan consistency and site alignment |
check_clock_tree | Checks clock tree structure and skew |
verify_connectivity | Verifies all net connections are correct |
verify_pg | Verifies power grid connectivity and EM |
verify_timing | Verifies timing closure across all corners |
verify_drc | Verifies zero DRC violations at signoff |
Typical Verification Flow Script
# === Typical Verification Flow ===
# After floorplan
check_floorplan > reports/floorplan_check.rpt
# After placement
check_placement > reports/placement_check.rpt
# After CTS
check_clock_tree > reports/cts_check.rpt
# After routing
check_route > reports/route_check.rpt
check_drc > reports/drc_check.rpt
# Final signoff verification
check_design > reports/design_check.rpt
check_timing > reports/timing_check.rpt
verify_connectivity > reports/connectivity.rpt
verify_pg > reports/pg_verify.rpt
verify_drc > reports/drc_signoff.rpt
verify_timing > reports/timing_signoff.rptCommand Deep-Dive: Understanding Each Command
What it is: check_design runs a comprehensive consistency check on the entire design database. It detects issues like unconnected pins, floating nets, missing libraries, hierarchy mismatches, and other structural problems that could cause downstream failures.
Where we use it: At the start of the flow after linking the design, and before every major step. Running check_design early catches problems before they waste compute time in later stages.
Syntax: check_design [-verbose] [-output <file>]
# Basic design check
check_design > reports/design_check.rpt
# Verbose design check
check_design -verbose > reports/design_check_detailed.rptWhat it is: check_timing validates the completeness and consistency of timing constraints. It identifies missing clock definitions, unconstrained paths, clock domain crossing (CDC) issues, and conflicting timing exceptions.
Where we use it: Before running STA to ensure constraints are complete. Unconstrained paths can hide real timing violations. This check ensures all registers have proper clock definitions and all I/O ports have delay constraints.
Syntax: check_timing [-verbose] [-include <checks>] [-output <file>]
# Full timing check
check_timing > reports/timing_check.rpt
# Check specific items
check_timing -include {no_clock unconstrained} > reports/timing_issues.rptWhat it is: verify_connectivity performs a comprehensive connectivity verification to ensure all nets are properly connected as specified in the netlist. It detects opens, shorts, and incorrect connections in the routed design.
Where we use it: After routing completion and before signoff. This is the equivalent of an LVS (Layout vs Schematic) check within the P&R tool. Connectivity violations must be resolved before tape-out.
Syntax: verify_connectivity [-type <type>] [-output <file>]
# Standard connectivity verification
verify_connectivity > reports/connectivity.rpt
# Detailed connectivity for specific nets
verify_connectivity -type all > reports/connectivity_detail.rptWhat it is: verify_pg verifies the power delivery network integrity including connectivity from pads to every cell, electromigration (EM) compliance, and IR drop analysis. It ensures all cells receive correct voltage levels.
Where we use it: After power grid creation and at signoff. PG verification catches missing power connections, insufficient via stacking, and current density violations that could cause chip failure.
Syntax: verify_pg [-net <net>] [-output <file>]
# Full PG verification
verify_pg > reports/pg_verify.rpt
# Verify specific power net
verify_pg -net VDD > reports/pg_vdd.rpt
verify_pg -net VSS > reports/pg_vss.rptWhat it is: verify_drc is the final signoff DRC verification that checks the routed design against all foundry design rules including spacing, width, minimum area, via enclosure, antenna, and metal density rules.
Where we use it: At final signoff after all DRC fixes are complete. Zero DRC violations are mandatory for tape-out. This command is more comprehensive than check_drc and uses foundry-certified rule decks.
Syntax: verify_drc [-waive <rules>] [-output <file>]
# Full DRC signoff verification
verify_drc > reports/drc_signoff.rpt
# DRC with specific rule waivers
verify_drc -waive {density_rule} > reports/drc_signoff.rptMastering these Verification commands is essential for achieving signoff quality. A design that passes all checks and verifications is ready for tape-out with confidence. Continue to Part 11: Miscellaneous Commands →