Tcl Reference Guide: Part 3 — Power Planning Commands

What it is: create_power_net creates a new power net (typically named VDD or VDD_CORE) in the design database. This net will carry the supply voltage from the I/O pads to all standard cells and macros. Multiple power nets can exist for different voltage domains.

Where we use it: Used at the start of power planning before building the power grid. You must create the power and ground nets before adding rings, stripes, or connecting them to cells. In multi-voltage designs each voltage island gets its own power net.

Syntax: create_power_net [-net <name>] [-voltage <value>]

# Create main core power net
create_power_net VDD

# Create separate power net for I/O domain
create_power_net VDD_IO

# Create power net for analog block
create_power_net VDD_ANA

What it is: create_ground_net creates a ground net (typically named VSS or GND) in the design database. This net provides the return path for current and serves as the reference voltage for all logic.

Where we use it: Always paired with create_power_net. Both power and ground nets must be created before building the PG network. In designs with multiple grounds (digital VSS, analog VSSA) you create separate ground nets.

Syntax: create_ground_net [-net <name>]

# Create main ground net
create_ground_net VSS

# Create separate ground for analog
create_ground_net VSS_ANA

# Create ground for I/O
create_ground_net VSS_IO

What it is: connect_pg_net connects power or ground nets to the PG pins of standard cells, macros, and I/O pads. This establishes the electrical connection between the supply network and the design components.

Where we use it: After creating the power and ground nets, you connect them to the design ports (chip-level VDD/VSS pads) and to the PG pins of all cells. Without this command the power grid is not electrically connected to the logic.

Syntax: connect_pg_net [-net <net_name>] [-cell_net <cell_net_name>] [-automatic]

# Connect power net to chip-level ports
connect_pg_net VDD -ports

# Connect ground net to chip-level ports
connect_pg_net VSS -ports

# Connect PG net to all cells
connect_pg_net VDD -cells
connect_pg_net VSS -cells

# Connect specific voltage domain
connect_pg_net VDD_ANA -domain ana_domain

What it is: add_ring creates power rings around the core area or around specific macro blocks. Rings are continuous loops of metal that surround the core and distribute current from the I/O pads to the stripes. Rings use thick upper metals for low resistance.

Where we use it: Power rings are typically added around the core perimeter and around large macros. The rings connect to the I/O pad power buses and feed the horizontal and vertical stripe network. Rings help reduce IR drop at the core boundaries.

Syntax: add_ring -net <net> -type <type> -width <value> -spacing <value> -layer <layer>

# Add VDD ring around core on M6
add_ring -net VDD -layer M6 -width 2.0 -spacing 0.5

# Add VSS ring around core on M7
add_ring -net VSS -layer M7 -width 2.0 -spacing 0.5

# Add ring around a specific macro
add_ring -net VDD -layer M6 -width 1.5 -around macro_inst

# Add ring with offset from core boundary
add_ring -net VDD -layer M6 -width 2.0 -offset 1.0

What it is: add_stripe creates power stripes which are parallel metal wires running across the core area. Stripes distribute current from the rings to individual standard cell rows. They are placed at regular intervals determined by the stripe pitch.

Where we use it: After adding rings you create stripes to cover the core area. Stripes alternate between VDD and VSS and use multiple metal layers (typically M4-M7) to create a mesh network. Stripe width and pitch are calculated based on current density and IR drop targets.

Syntax: add_stripe -net <net> -layer <layer> -width <value> -spacing <value> -set_to_set <value>

# Add horizontal VDD stripes on M4
add_stripe -net VDD -layer M4 -width 1.0 -spacing 5.0 -pitch 50.0 -direction horizontal

# Add vertical VSS stripes on M5
add_stripe -net VSS -layer M5 -width 1.0 -spacing 5.0 -pitch 50.0 -direction vertical

# Add staggered stripes for better coverage
add_stripe -net VDD -layer M6 -width 2.0 -pitch 100.0 -offset 25.0

What it is: add_rail_connection connects the power grid to the standard cell rails on the lowest metal layer (M1). Standard cells have predefined VDD and VSS rails at their top and bottom edges and this command stitches the stripe network down to those rails.

Where we use it: After the rings and stripes are created you add rail connections to ensure every standard cell row receives power. The rails run horizontally on M1 and connect to the stripes through vias. This is the final connection step before power grid verification.

Syntax: add_rail_connection -net <net> -layer <layer> -width <value>

# Connect VDD rails to standard cell rows
add_rail_connection -net VDD -layer M1

# Connect VSS rails to standard cell rows
add_rail_connection -net VSS -layer M1

# Set rail width and spacing
add_rail_connection -net VDD -layer M1 -width 0.5

What it is: add_via_array places via arrays (groups of vias) to connect power stripes between different metal layers. A single via may have high resistance so via arrays use multiple parallel vias to reduce resistance and improve electromigration (EM) reliability.

Where we use it: At every junction where a power stripe on one metal layer connects to a stripe on another layer. For example where an M4 stripe connects to an M6 stripe you add a via array. More vias means lower resistance and better current handling.

Syntax: add_via_array -net <net> -cut_size <value> -pattern <pattern>

# Add via array at stripe intersections
add_via_array -net VDD -from M4 -to M6 -rows 4 -columns 4

# Add via array for high-current paths
add_via_array -net VDD -from M6 -to M7 -rows 8 -columns 8

# Add via with specific spacing
add_via_array -net VSS -from M4 -to M5 -rows 2 -columns 2 -spacing 0.5

What it is: create_power_domain defines a power domain which is a group of cells that share the same power supply. Power domains enable voltage scaling and power gating where different blocks of the chip can operate at different voltages or be shut off independently.

Where we use it: In multi-voltage designs you create separate power domains for each voltage island. The core logic may run at 0.8V while I/O runs at 1.8V and memory runs at 1.1V. Each domain has its own power grid and supply connections.

Syntax: create_power_domain -name <domain_name> -voltage <value>

# Create core power domain
create_power_domain CORE_DOMAIN -voltage 0.8

# Create I/O power domain
create_power_domain IO_DOMAIN -voltage 1.8

# Create memory power domain
create_power_domain MEM_DOMAIN -voltage 1.1

What it is: report_power_grid prints a detailed summary of the power grid including ring dimensions, stripe patterns, via arrays, power domains, and connectivity. It is the primary verification command for the PDN.

Where we use it: After building the power grid run this to verify all layers are connected correctly. Check that rings and stripes exist on the intended layers, via arrays are present at layer transitions, and all power domains are properly connected. Also run check_pg to detect floating nets or missing connections.

Syntax: report_power_grid [-net <net>] [-verbose] [-output <file>]

# Basic power grid report
report_power_grid > reports/power_grid.rpt

# Detailed report with all layers
report_power_grid -layers all > reports/pg_layers.rpt

# Report power domain summary
report_power_grid -domains > reports/pg_domains.rpt

# Check PG for violations
check_pg > reports/pg_check.rpt