STA Interview Questions - Part 1: Timing Basics

Q1 What is Static Timing Analysis (STA)?

Static Timing Analysis (STA) is a method of validating the timing performance of a digital circuit without requiring input stimuli. Unlike dynamic simulation, STA exhaustively checks all possible paths for setup and hold violations by analyzing the circuit topology. It uses delay models for standard cells and interconnects to compute arrival times at each node, then compares them against required times based on clock constraints. STA is the primary signoff method for timing closure in ASIC/SoC flows.

Q2 Define setup time. Why is it important?

Setup time is the minimum amount of time that input data must be stable before the active clock edge. If data transitions within the setup window, the flip-flop may enter a metastable state. Setup violations limit the maximum operating frequency of a design. The setup condition is captured by the equation:

T_clk_q + T_combo + T_setup <= T_period + T_skew

where T_clk_q is clock-to-Q delay, T_combo is combinational logic delay, T_setup is the flop's setup requirement, T_period is the clock period, and T_skew is useful skew.

Q3 Define hold time. Why is it important?

Hold time is the minimum amount of time that input data must remain stable after the active clock edge. If data changes too soon after the clock edge, the flip-flop may capture incorrect data. Hold violations are independent of clock frequency — they occur due to fast data paths relative to clock paths. The hold condition equation is:

T_clk_q_min + T_combo_min >= T_hold + T_hold_skew

Hold violations are typically fixed by adding delay through buffer insertion in the data path.

Q4 Derive the setup timing equation with clock skew.

The setup timing equation ensures that data launched from one flop arrives at the next flop early enough before the capturing clock edge:

Data arrival time: T_clk_q + T_combo
Data required time: T_period + T_skew - T_setup
Setup slack = T_period + T_skew - T_setup - (T_clk_q + T_combo)

For a path from FF1 to FF2, T_skew = T_capture_clock - T_launch_clock. Positive skew (capture clock arrives later) helps setup but hurts hold. Negative skew (capture clock arrives earlier) hurts setup but helps hold. Setup slack must be ≥ 0 for the path to meet timing.

Q5 Derive the hold timing equation with clock skew.

The hold timing equation ensures that data launched from one flop does not arrive at the next flop too early, overwriting previous data:

Data arrival time (hold): T_clk_q_min + T_combo_min
Data required time (hold): T_hold + T_skew
Hold slack = (T_clk_q_min + T_combo_min) - (T_hold + T_skew)

Note the min delays — hold analysis uses fastest process, highest voltage, and highest temperature corners (or lowest for the particular technology). Hold slack must be ≥ 0. Inserting buffers on the data path increases T_combo_min, fixing hold violations.

Q6 What is clock skew? Explain positive and negative skew.

Clock skew is the difference in arrival time of the same clock edge at different flip-flops. It is caused by wire delays, buffer imbalances, and process variations:

Positive skew — The capture clock arrives later than the launch clock. This helps setup timing (more time for data to propagate) but hurts hold timing.
Negative skew — The capture clock arrives earlier than the launch clock. This hurts setup timing but helps hold timing.

Designers use useful skew deliberately to fix setup violations by intentionally adding delay to capture clock paths.

Q7 What is clock jitter? How does it affect timing?

Clock jitter refers to short-term, cycle-to-cycle variations in clock edge position. It is caused by PLL noise, power supply noise, and thermal effects. Jitter is typically specified as a Â± value (e.g., Â±20 ps). In STA, jitter reduces the effective clock period for setup analysis. The setup equation with jitter becomes:

T_clk_q + T_combo + T_setup <= T_period - T_jitter + T_skew

Jitter does not affect hold timing because it affects both launch and capture edges on the same cycle for hold checks.

Q8 Differentiate between clock skew and clock jitter.

Aspect	Clock Skew	Clock Jitter
Nature	Systematic (spatial)	Random (temporal)
Cause	Wire delays, buffer mismatch, process variation	PLL noise, supply noise, thermal effects
Affects	Both setup and hold	Setup only (reduces effective period)
Predictability	Deterministic (can be calculated)	Statistical (specified as range)
Mitigation	Clock tree balancing, useful skew	Lower-jitter PLL, decoupling caps

Q9 What are the four types of timing paths in STA?

STA categorizes paths into four types based on their start and end points:

Input-to-Register — Starts at a primary input, ends at a flip-flop data pin. Constrained by set_input_delay.
Register-to-Register — Starts at a flip-flop clock pin, passes through combinational logic, ends at another flip-flop data pin. This is the most common path type.
Register-to-Output — Starts at a flip-flop clock pin, ends at a primary output. Constrained by set_output_delay.
Input-to-Output — Starts at a primary input, passes through combinational logic, ends at a primary output. Rare in synchronous designs.

Each path type is analyzed for both max (setup) and min (hold) timing conditions.

Q10 What is positive slack and negative slack in STA?

Slack is the margin between the required time and the arrival time of a signal. It indicates whether a timing path meets its constraint:

Positive slack — Data arrives earlier (setup) or later (hold) than required. The path meets timing. Positive slack indicates the design can potentially operate at a higher frequency (for setup) or has margin.
Negative slack — Data arrives too late (setup) or too early (hold). The path violates timing. The worst negative slack (WNS) determines the maximum achievable frequency. Total negative slack (TNS) sums all negative slack values across violating paths.

Negative setup slack requires redesign (faster logic, pipelining, or lower frequency). Negative hold slack requires buffer insertion to add delay.