Physical Design Interview Questions - Part 1: Floorplanning & Placement

The PD flow consists of: 1) Floorplanning — defining chip area, macro placement, I/O pins; 2) Power Planning — building the power distribution network; 3) Placement — placing standard cells; 4) Clock Tree Synthesis (CTS) — building clock network; 5) Routing — connecting all cells; 6) Physical Verification — DRC/LVS checks; 7) Timing Signoff — STA closure; 8) GDSII generation for tape-out.

Floorplanning is the first PD step where the chip area is organized. Key goals: determine die size and aspect ratio, place hard macros (SRAM, PLLs), define I/O pad locations, plan power grid, and estimate routing resources. Good floorplanning reduces congestion and improves timing closure.

Placement goals: minimize total wirelength for lower delay and power, reduce routing congestion, meet timing constraints, avoid DRC violations, and ensure routability. Modern placers optimize for multiple objectives simultaneously using analytical placement algorithms.

Global placement roughly distributes cells across the die to minimize wirelength while allowing overlaps. Detailed placement removes overlaps (legalization) and performs local optimizations like cell swapping and spacing to improve timing and reduce congestion without moving cells far.

Soft macros are synthesizable RTL — flexible, can be optimized for different technologies, but need full physical implementation. Hard macros have fixed layout (e.g., SRAM, PLL, SERDES) — pre-optimized for power/performance but inflexible and process-specific.

Congestion occurs when routing demand exceeds available tracks. Causes: high cell density, complex pin access, too many nets in a region, poor floorplanning. Fixes: spreading cells (increased placement utilization margin), optimizing floorplan, moving macros, using higher metal layers, or reducing cell count via logic synthesis.

I/O pads are placed based on: package type and ball map, signal integrity requirements (separate noisy I/O from sensitive), power pad distribution for IR drop, clock pad location for minimal skew, and die-edge constraints. Mixed-signal designs require strict analog/digital pad separation.

The power grid distributes VDD/VSS across the chip through stacked metal stripes and vias. Design considerations: electromigration limits (current density), IR drop targets (<5% of VDD), routing resource usage, and clock shielding. Grid topology includes stripes, rings, and straps at multiple metal layers.

Tap cells connect the substrate (p-well to VSS, n-well to VDD) to prevent latch-up. They provide well/substrate bias contacts and are inserted periodically (every 20-50 microns) across the standard cell area. Without tap cells, parasitic bipolar transistors can trigger latch-up.

Die area is estimated as: (total standard cell area + macro area) / utilization target. Utilization typically ranges from 60-80% depending on design complexity. Additional area is reserved for power grid, clock distribution, I/O pads, and routing channels. Aspect ratio is chosen based on package and performance requirements.