Physical Design Interview Questions - Part 3: Power & Signoff

IR drop is the voltage drop along the power distribution network due to wire resistance (V = I × R). Excessive IR drop reduces cell drive strength and increases delay, causing timing failures. Static IR drop is average current draw; dynamic IR drop captures peak current events and is more severe.

Electromigration is the gradual displacement of metal atoms due to high current density, eventually causing open circuits or shorts. Foundries provide current density limits per metal layer. Managed by: widening high-current wires, using multiple vias, limiting wire length, and running EM analysis at signoff.

Power gating uses sleep transistors (header/footer) to shut off power to idle blocks, reducing leakage power. Challenges: wake-up time (inrush current spike), state retention (isolation cells needed), power switch sizing, and dynamic IR drop during wake-up.

LVT (low-Vt): fast, high leakage — used on timing-critical paths. SVT (standard-Vt): balanced speed/leakage. HVT (high-Vt): slow, low leakage — used on non-critical paths. Multi-Vt optimization replaces cells on non-critical paths with HVT to reduce leakage without impacting timing.

Pre-CTS timing uses ideal clocks (zero skew, estimated latency) and wire load models. Post-CTS timing uses propagated clocks (actual buffer delays, real skew), extracted RC parasitics, and provides accurate timing. Post-CTS results always differ from pre-CTS.

Flat PD implements the entire design as one block — simpler but limited by tool capacity (~10M gates). Hierarchical PD partitions the design into blocks implemented independently with boundary constraints — scalable for large SoCs but requires more planning for timing and power at top level.

GDSII (Graphic Design System II) is the standard binary format for IC layout data sent to foundry. It contains: geometric shapes (polygons, paths, circles), layer numbers, structures/cells, and placement coordinates. The final GDSII is verified through DRC/LVS before tape-out.

The power grid must: deliver uniform VDD/VSS across the chip, meet IR drop targets (<3-5% of VDD), handle peak current without electromigration, minimize routing resource usage, and provide adequate decoupling capacitance. Grid analysis is iterative during PD.

Multi-voltage design uses multiple voltage domains to save power. Extra cells needed: level shifters (convert between voltage domains), isolation cells (block X-states when a domain is off), and always-on cells/buffers for power management logic.

Timing signoff checks: all setup/hold violations fixed (positive slack), no false path violations, clock skew within limits, no clock gating check violations, timing across all PVT corners passes, no asynchronous clock domain violations, and STA reports clean with all constraints validated.