STA Interview Questions - Part 2: SDC Constraints

SDC (Synopsys Design Constraints) is the industry-standard Tcl-based format for specifying design constraints, including timing, area, and power. The SDC file tells the synthesis and STA tools about clock definitions, input/output delays, timing exceptions, and design rules. It ensures the tool optimizes the design correctly and verifies that timing is met. The read_sdc command loads constraints into the tool during synthesis and signoff STA flows.

The create_clock command defines a clock source in the design:

create_clock -name clk -period 10 [get_ports clk_in]
create_clock -name clk_div2 -period 20 -waveform {0 10}

Key parameters: -name (clock name), -period (clock period in ns), -waveform (rising/falling edge times, default 0 and period/2), and the source pins/ports. Multiple waveforms can define non-50% duty cycles. The period is the fundamental constraint — all path timing is derived from it.

set_input_delay specifies the arrival time of data at an input port relative to the clock. It models the delay from the external device's clock edge to the input pin. set_output_delay specifies the time required by the external device after the clock edge for data at an output port:

set_input_delay -max 2.5 -clock clk [get_ports data_in]
set_output_delay -min 1.0 -clock clk [get_ports data_out]

-max indicates the latest arrival (setup check), -min indicates the earliest arrival (hold check). These values come from the external device's timing specifications (T_co_max, T_co_min, T_setup, T_hold of the external chip).

set_false_path disables timing analysis on specific paths that are not relevant for timing. Common use cases:

# Async-crossing: no timing relationship
set_false_path -from [get_clocks clk_a] -to [get_clocks clk_b]

# Slow control signal (test mode)
set_false_path -from [get_ports test_mode]

# Reset path (not timed)
set_false_path -through [get_pins reg*/RN]

# Initialization path
set_false_path -from [get_pins pll_lock]

Using false paths incorrectly (when a path actually needs timing) can lead to functional failures. Only paths guaranteed to never affect timing should be false-pathed.

set_multicycle_path (MCP) informs the tool that a path is allowed more than one clock cycle. By default, STA assumes all paths are single-cycle:

# Path takes 2 cycles
set_multicycle_path -setup 2 -from [get_pins U1/Q] -to [get_pins U2/D]
set_multicycle_path -hold 1 -from [get_pins U1/Q] -to [get_pins U2/D]

When -setup is set to N, the setup check uses the N-th clock edge instead of the first. The -hold option must be set to N-1 to shift the hold check correctly. MCPs are common for slow enable paths, memory read operations, and pipelined interfaces where data validity spans multiple cycles.

set_max_delay and set_min_delay override the default timing analysis with a user-specified delay limit:

set_max_delay 15 -from [get_ports A] -to [get_ports B]
set_min_delay 2  -from [get_ports A] -to [get_ports B]

These differ from set_false_path because they still perform timing analysis but with custom limits. Use them for: (1) combinatorial paths without a clock reference, (2) asynchronous interface constraints, (3) paths where the default clock-based analysis is inappropriate. False paths disable analysis entirely — use that only when the path truly does not matter for timing.

set_clock_groups defines relationships between clock domains. It simplifies handling of asynchronous clock domain crossings (CDCs):

set_clock_groups -asynchronous \
  -group [get_clocks {clk_a clk_a_div2}] \
  -group [get_clocks {clk_b}] \
  -group [get_clocks {clk_c}]

This is functionally equivalent to setting false paths between the groups, but is more readable and maintainable. Options: -asynchronous (no timing relationship), -physically_exclusive (clocks that never coexist), -logically_exclusive (clocks that are mutually exclusive by design muxing).

create_generated_clock defines a clock derived from a master clock through clock dividers, multipliers, or muxes. Unlike create_clock, which creates an independent clock source, generated clocks derive their timing characteristics from a source clock:

create_generated_clock -name clk_div4 \
  -source [get_ports clk_in] \
  -divide_by 4 [get_pins clk_div_reg/Q]

create_generated_clock -name clk_mul2 \
  -source [get_pins pll/clk_out] \
  -multiply_by 2 [get_pins dll/clk_out]

The -divide_by and -multiply_by options define the frequency relationship. -edges can specify custom edge relationships. Generated clocks automatically track source clock jitter and latency.

Clock latency is the total delay from the clock source to a sequential element's clock pin. It consists of:

• Source latency — Delay from the external clock source (PLL input, crystal) to the clock port/pin of the chip. This is also called insertion delay from the package/board.
• Network latency — Delay from the clock port (the entry point into the design) to the flip-flop clock pin. This is the delay through the clock distribution network (clock tree).

set_clock_latency -source 2.0 [get_clocks clk]   ;# source latency
set_clock_latency 1.5 [get_clocks clk]            ;# network latency

Total latency = source latency + network latency. After CTS, network latency is replaced by the actual propagated clock delay.

set_clock_uncertainty accounts for non-ideal clock behavior that cannot be explicitly modeled. It captures jitter, PLL tracking error, and margin:

# Setup uncertainty (reduces available time)
set_clock_uncertainty -setup 0.2 [get_clocks clk]

# Hold uncertainty (reduces hold margin)
set_clock_uncertainty -hold 0.05 [get_clocks clk]

# For inter-clock paths
set_clock_uncertainty -from clk_a -to clk_b -setup 0.5

Setup uncertainty subtracts from the available period (making timing harder to meet). Hold uncertainty adds to the hold requirement. Typical values: 50–200 ps for intra-domain, larger for inter-domain paths. Some flows use set_clock_uncertainty to add designer margin for safety.