Part 7 of the Tcl command reference covering Timing Constraint commands used in Static Timing Analysis (STA) and SDC constraint development. These commands define clock specifications, I/O delays, timing exceptions, and reporting for signoff timing closure in ICC2 and Innovus flows.
The complete physical design flow follows this order:
- Design & Database Setup
- Floorplanning
- Power Planning
- Placement
- Clock Tree Synthesis
- Routing
- Optimization
- Signoff & Reports
Quick Reference: Timing Constraint Commands for EDA Tools
Timing constraints drive the entire static timing analysis (STA) engine. The Synopsys Design Constraints (SDC) format is the industry standard for specifying timing intent. These commands define clocks, I/O timing, false paths, multicycle paths, and generate the timing reports used for signoff.
| Command | Description |
|---|---|
create_clock | Creates a clock definition |
create_generated_clock | Creates a generated clock (derived from master clock) |
set_input_delay | Sets input arrival time relative to clock |
set_output_delay | Sets output required time relative to clock |
set_max_delay | Sets maximum delay constraint on a path |
set_min_delay | Sets minimum delay constraint on a path |
set_multicycle_path | Sets multicycle path exception (MCP) |
set_false_path | Sets false path exception (no timing required) |
set_case_analysis | Sets case analysis for mode-specific timing |
set_disable_timing | Disables timing through a cell or pin |
set_clock_groups | Groups clocks as asynchronous or exclusive |
set_clock_uncertainty | Sets clock uncertainty (jitter + margin) |
set_clock_latency | Sets clock latency (source or network) |
report_timing | Reports timing of specified paths |
report_timing_summary | Reports timing summary statistics |
report_tns | Reports Total Negative Slack |
report_wns | Reports Worst Negative Slack |
report_timing_paths | Reports multiple timing paths |
check_timing | Checks timing constraint completeness |
Typical SDC Constraint Script
# === Typical SDC Constraint Flow ===
# Define clocks
create_clock -name clk -period 10.0 [get_ports clk]
create_generated_clock -name clk_div2 -divide_by 2 \
-source [get_ports clk] [get_pins divider/out]
# Set clock uncertainty and latency
set_clock_uncertainty -setup 0.2 [get_clocks clk]
set_clock_uncertainty -hold 0.05 [get_clocks clk]
set_clock_latency -source 0.5 [get_clocks clk]
# Set I/O delays
set_input_delay -clock clk 2.0 [get_ports data_in]
set_output_delay -clock clk 1.5 [get_ports data_out]
# Timing exceptions
set_false_path -from [get_clocks clk_a] -to [get_clocks clk_b]
set_multicycle_path -setup 2 -from [get_pins slow_path/reg/CK]
# Report timing
report_timing > reports/timing.rpt
report_timing_summary > reports/timing_summary.rpt
report_tns > reports/tns.rpt
report_wns > reports/wns.rptCommand Deep-Dive: Understanding Each Command
What it is: create_clock defines a clock in the design with a period, waveform, and source pin or port. This is the fundamental timing constraint that drives STA. Every sequential element is timed relative to its clock edge.
Where we use it: At the top-level clock input ports or PLL output pins. The clock period determines the available time for logic. For multi-frequency designs, create separate clocks and define their relationships with set_clock_groups.
Syntax: create_clock -name <name> -period <value> [-waveform {rise fall}] <source>
# Create a 100MHz clock
create_clock -name clk -period 10.0 [get_ports clk]
# Virtual clock for input/output delays
create_clock -name vclk -period 5.0
# Clock with non-50% duty cycle
create_clock -name clk -period 10.0 -waveform {0 3} [get_ports clk]What it is: set_input_delay specifies the arrival time of a signal at an input port relative to the clock. set_output_delay specifies the required time for a signal at an output port before the next clock edge. These model the external timing environment.
Where we use it: For all chip I/O ports. Input delay represents the external logic delay plus board trace delay. Output delay represents the external register setup requirement. Both are critical for interface timing closure.
Syntax: set_input_delay -clock <clock> [-max <value>] [-min <value>] <port_list> / set_output_delay -clock <clock> [-max <value>] [-min <value>] <port_list>
# Input delay - max for setup, min for hold
set_input_delay -clock clk -max 2.5 [get_ports data_in]
set_input_delay -clock clk -min 0.5 [get_ports data_in]
# Output delay
set_output_delay -clock clk -max 1.8 [get_ports data_out]
set_output_delay -clock clk -min 0.3 [get_ports data_out]
# With rise/fall specific delays
set_input_delay -clock clk -rise 2.0 [get_ports addr]What it is: set_multicycle_path adjusts the number of clock cycles allowed for a timing path. By default, all paths are single-cycle (setup checked in 1 cycle, hold in 0 cycles). Multicycle paths (MCP) relax this for paths that intentionally take multiple cycles.
Where we use it: For slow logic paths, enable signals, or clock domain crossings where data is expected to arrive after multiple clock cycles. The -setup option sets the launch edge and -hold adjusts accordingly.
Syntax: set_multicycle_path [-setup <n>] [-hold <n>] [-from <list>] [-to <list>]
# 2-cycle setup path (data arrives after 2 clocks)
set_multicycle_path -setup 2 -from [get_pins slow_reg/CK]
# 1-cycle hold (default after -setup 2)
set_multicycle_path -hold 1 -from [get_pins slow_reg/CK]
# MCP between clock domains
set_multicycle_path -setup 2 \
-from [get_clocks clk_a] -to [get_clocks clk_b]What it is: set_false_path declares that a timing path does not need to meet timing constraints. The STA tool ignores these paths entirely. Common examples include test mode paths, reset paths, and asynchronous clock domain crossings with synchronizers.
Where we use it: For paths that are not timing-critical due to design intent. Be careful not to overuse false paths as they can hide real timing issues. Always verify false paths are truly not required for proper functionality.
Syntax: set_false_path [-from <list>] [-to <list>] [-through <list>]
# False path between asynchronous clock groups
set_false_path -from [get_clocks clk_a] -to [get_clocks clk_b]
# False path through test mode
set_false_path -from [get_ports scan_enable]
# False path to/from specific cells
set_false_path -through [get_pins async_sync/D]What it is: set_clock_groups defines relationships between clock domains. Clocks can be asynchronous (no timing relationship, equivalent to false paths), exclusive (mutually exclusive in operation modes), or physically exclusive.
Where we use it: For multi-clock designs. Asynchronous groups disable timing paths between unrelated clock domains. Exclusive groups are used when clocks never operate together, like functional and scan mode clocks.
Syntax: set_clock_groups [-asynchronous] [-exclusive] -group <list> -group <list>
# Asynchronous clock groups
set_clock_groups -asynchronous \
-group [get_clocks clk_a] \
-group [get_clocks clk_b]
# Exclusive groups (functional vs test)
set_clock_groups -exclusive \
-group [get_clocks {func_clk}] \
-group [get_clocks {scan_clk}]What it is: report_timing generates detailed timing reports for specified paths showing the arrival time, required time, slack, and the delay breakdown by stage. It is the primary command for timing analysis and debug.
Where we use it: Throughout the design flow after placement, CTS, and routing to verify timing closure. Use report_timing_summary for high-level metrics, report_tns for total negative slack, and report_wns for worst negative slack.
Syntax: report_timing [-delay_type <type>] [-max_paths <n>] [-nworst <n>] [-output <file>]
# Report worst setup timing paths
report_timing -max_paths 10 -nworst 5 > reports/setup.rpt
# Report hold timing paths
report_timing -delay_type min > reports/hold.rpt
# Report timing summary
report_timing_summary > reports/summary.rpt
# Report TNS and WNS
report_tns > reports/tns.rpt
report_wns > reports/wns.rptMastering these Timing Constraint commands is essential for STA closure. Proper constraints ensure that all paths are correctly analyzed and timing violations are identified before tape-out. This concludes the Tcl Command Reference series covering the full physical design flow from database setup to signoff timing analysis.