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SystemVerilog Interview Questions - Part 2: Randomization & Coverage

May 18, 2026 HDL2Chips Team SystemVerilog

This part covers randomization, constraints, and functional coverage in SystemVerilog. These are core concepts for constrained-random verification.

Q11 What is the difference between rand and randc?

rand declares a variable that is randomly assigned a value within its range each time randomize() is called, with no guarantee of across-call uniqueness. randc (random cyclic) iterates through all possible values in a cycle before repeating any value. Once all values in the cycle have been generated, the cycle restarts. randc is useful for scenarios like walking through all addresses exhaustively.

Q12 How do constraint blocks work in SystemVerilog?

Constraint blocks are defined inside a class using the constraint keyword. They specify relationships and ranges that random variables must satisfy. Constraints can be simple (e.g., addr inside {[0:255]}), relational (e.g., addr > 16), or involve multiple variables. Constraints can be turned on/off using constraint_mode(). Multiple constraint blocks can exist and are solved simultaneously by the solver.

class Packet;
  rand bit [7:0] addr;
  rand bit [7:0] data;
  constraint addr_range { addr inside {[16:240]}; }
  constraint data_valid { data != 8'h00; }
endclass
Q13 Explain inside and dist constraints.

inside {} restricts a random variable to a set of values or ranges, e.g., addr inside {[0:15], [32:47], 255}. dist assigns weighted distribution to values or ranges. := gives equal weight to each value in the range, while :/ distributes the total weight evenly across all values.

constraint c_dist {
  addr dist { 0 := 1, [1:254] :/ 50, 255 := 1 };
}
Q14 What are implication constraints?

Implication constraints use the -> operator to create conditional constraints: if the left-hand side is true, the right-hand side must also be true. For example, constraint c { (addr == 0) -> (data == 8'hFF); } means if addr is 0, then data must be 8'hFF. If the left-hand side is false, the constraint is not active.

Q15 Compare $urandom and $urandom_range.

$urandom generates a random 32-bit unsigned integer. It can be seeded with an optional argument. $urandom_range(min, max) returns a random unsigned integer within the inclusive range [min, max]. Both are system functions and not class methods. For class-based randomization, use randomize() with constraint blocks instead.

Q16 What is covergroup and coverpoint in SystemVerilog?

A covergroup encapsulates a set of coverage points and options. A coverpoint defines a coverage point on a variable or expression, automatically creating bins for each value. Coverage groups can be instantiated in classes or modules and can be sampled explicitly with the .sample() method or automatically.

covergroup cg_packet @(posedge clk);
  addr_cp : coverpoint pkt.addr;
  data_cp : coverpoint pkt.data;
endgroup
Q17 Explain the different types of bins: auto, ignore, and illegal.

Auto bins are automatically created by the tool for each value. bins can also be explicitly defined to group values: bins low = {[0:63]};. ignore_bins excludes specified values from coverage measurement, meaning they do not affect coverage percentage. illegal_bins cause a runtime error if hit during simulation, signaling a testbench or DUT issue that should never occur.

Q18 What is cross coverage in SystemVerilog?

Cross coverage measures the coverage of combinations of values across two or more coverpoints using the cross keyword. The cross product creates bins for each combination. It is useful for verifying that specific combinations of inputs or states have been exercised.

covergroup cg;
  addr_cp : coverpoint pkt.addr;
  data_cp : coverpoint pkt.data;
  addr_data_cross : cross addr_cp, data_cp;
endgroup
Q19 How does the randomize() method work?

randomize() is a built-in method available for all class objects. It assigns random values to all rand and randc variables in the class, subject to active constraint blocks. It returns 1 if successful and 0 if the solver cannot find a valid solution (constraint contradiction). It can also be called with inline constraints: pkt.randomize() with { addr == 10; }.

Q20 What are pre_randomize and post_randomize?

pre_randomize() is a built-in callback function called before every randomize() call. It can be overridden to set up preconditions or save state. post_randomize() is called after successful randomization and is commonly used to compute derived values, update reference models, or display randomized values.

function void post_randomize();
  $display("Randomized: addr=%0h data=%0h", addr, data);
endfunction

Randomization and coverage drive modern constrained-random verification. Continue to Part 3 for interfaces, assertions, and UVM basics.