Physical Design Interview Questions - Part 2: CTS & Routing

CTS builds a clock distribution network to deliver the clock from the source to all sequential elements (flip-flops, latches). Goals: minimize clock skew, meet insertion delay targets, reduce power consumption, and minimize clock jitter. Common topologies include H-tree, balanced tree, and mesh networks.

Clock skew is minimized by balancing path lengths and buffer delays to all sink pins. CTS tools use techniques like: matched delay buffers, clock tree balancing algorithms, useful skew (intentional skew to fix timing), and shielding to reduce crosstalk impact on clock nets.

Global routing partitions the chip into routing tiles (GCells) and plans approximate paths for all nets without assigning specific tracks. Detailed routing assigns actual metal tracks, vias, and wire widths, creating the physical wires while checking DRC rules in real time.

DRC verifies the layout complies with foundry design rules: minimum spacing between wires, minimum width, minimum enclosure, via rules, and antenna rules. DRC violations (markers) must be fixed before tape-out to ensure manufacturability.

Layout vs. Schematic (LVS) checks that the physical layout matches the original gate-level netlist. It verifies: device recognition (transistors, diodes), connectivity (nets match), device sizes (W/L ratios). LVS must pass clean before tape-out.

During plasma etching, long metal wires act as antennas collecting charge that can damage transistor gates. Fixes: insert antenna diodes to provide a discharge path, use jumper routing (break long metal segments with higher layer metal), or add buffer insertion to limit wire segment length.

Standard Parasitic Exchange Format (SPEF) contains extracted RC parasitics for each net — resistance (R), capacitance (C), and coupling capacitance (Cc). STA tools read SPEF for accurate post-layout timing analysis. It includes wire resistance, via resistance, and ground/coupling capacitance values.

Filler cells are empty cells placed in gaps between standard cells to maintain continuity of the power grid (VDD/VSS rails) and well layers (N-well/P-well). They do not implement logic but ensure DRC compliance across the row. Decap filler cells also add decoupling capacitance.

Engineering Change Order (ECO) is a late-stage design change. Metal-only ECO changes only top metal layers to fix bugs without re-spinning lower layers (cheaper). Functional ECO adds/deletes standard cells to implement logic changes. ECOs are minimized due to mask cost.

Scan chains connect flip-flops into shift registers for manufacturing test. Flip-flops are replaced with scan flip-flops (with MUX) and connected in series. Scan insertion can be done pre-placement (RTL) or post-placement. The scan chain order affects routing congestion.