Master Verilog & SV

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Basic Gates

Implement fundamental logic operations using structural and behavioral modeling.

Combinational

Design complex data routing circuits using Muxes, Decoders, and Arithmetic Units.

Sequential

Explore time-dependent logic with Flip-Flops, Latches, and synchronized circuits.

Shift Registers

Implement high-speed data serialization and parallel-to-serial conversion logic.

FSM

Architect robust Finite State Machines for complex control logic and protocol handling.

Counters

Design efficient Binary, Gray, and Ring counters for timing and control applications.

Waveform

Analyze timing diagrams, detect glitches, and master setup/hold timing analysis.

Fundamentals of Verilog

Master Verilog HDL from scratch covering gates, combinational circuits, sequential logic, counters, shift registers and FSMs.

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D Flip-Flop

Medium

Problem Statement

Build a module that captures the sensor value at the clock tick and holds it until the next tick. When the clock rises, q takes d. Between ticks, q stays unchanged.

Input/Output Examples:

clk=0, d=0 -> q=0
clk=0, d=1 -> q=0 (mid-cycle change ignored)
clk=↑, d=1 -> q=1
clk=0, d=0 -> q=1 (still holds)

Constraints

Module name: top
Inputs: clk, d (1-bit each)
Output: q (1-bit)
Use always @(posedge clk)
Use non-blocking assignment (<=)

Execution Output

Console ready. Click Run or Submit to see outputs...

SIGNAL VALUE

clk 0

d 0

q 1

No Waveform Yet

Click ▶ Run to compile your code
and generate the signal waveform.

Verilog

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module top (
    input  clk,
    input  d,
    output reg q
);

    // Write code here...

endmodule

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