Master Verilog & SV
HDL2Chips is the premier interview prep platform for hardware engineers. Solve industry-standard FPGA and ASIC design problems.
Basic Gates
Implement fundamental logic operations using structural and behavioral modeling.
Combinational
Design complex data routing circuits using Muxes, Decoders, and Arithmetic Units.
FSM
Architect robust Finite State Machines for complex control logic and protocol handling.
Shift Registers
Implement high-speed data serialization and parallel-to-serial conversion logic.
Counters
Design efficient Binary, Gray, and Ring counters for timing and control applications.
Sequential
Explore time-dependent logic with Flip-Flops, Latches, and synchronized circuits.
Waveform
Analyze timing diagrams, detect glitches, and master setup/hold timing analysis.
Fundamentals of Verilog
Master Verilog HDL from scratch covering gates, combinational circuits, sequential logic, counters, shift registers and FSMs.
Experience our Pro IDE
D Flip-Flop
MediumProblem Statement
Build a module that captures the sensor value at the clock tick and holds it until the next tick. When the clock rises, q takes d. Between ticks, q stays unchanged.
clk=0, d=0 -> q=0 clk=0, d=1 -> q=0 (mid-cycle change ignored) clk=↑, d=1 -> q=1 clk=0, d=0 -> q=1 (still holds)
Constraints
- Module name: top
- Inputs: clk, d (1-bit each)
- Output: q (1-bit)
- Use
always @(posedge clk) - Use non-blocking assignment (
<=)
No Waveform Yet
Click ▶ Run to compile your code
and generate the signal waveform.
module top (
input clk,
input d,
output reg q
);
// Write code here...
endmoduleWhat engineers say about HDL2Chips
"The Fundamentals of Verilog course was very helpful and easy to understand. The explanations, examples, and exercises made learning Verilog and FSM design much easier. I especially liked the hands-on coding practice."
"Completed 30 problems focusing on core Verilog and digital logic concepts. This practice strengthened my understanding of how digital circuits are described using HDL and improved my RTL design thinking."
"Successfully completed the HDL2Chips Logic Design Program with 200+ Verilog problems. The hands-on approach significantly strengthened my understanding of RTL design principles and digital system design."
"Successfully completed all 130 problems in the Basic Logic Gates track. The hands-on practice strengthened my foundation in Verilog and sharpened my understanding of Boolean logic and HDL coding."
"The concepts were explained clearly with relevant examples, making it easier to understand and apply. The hands-on exercises helped reinforce learning effectively."
"It has been very helpful for me to improve my syntax and debugging skills. Thank you for creating such a useful platform!"
"I liked the way it explained each concept before the problem. Keynotes helped me revise a few concepts. I will definitely recommend this to my juniors."
"The UI is absolutely good and the quality of this platform is at its peak."
"I learned the proper basics and advanced level in Verilog, and also learned how to analyze waveforms effectively."
"Very helpful. Thanks for providing this at free of cost."
"The one and only web for mastering Verilog."
Master the skills for top-tier hardware roles.
Interactive Waveforms
High-contrast, zoomable signal viewing—just like industry-standard logic analyzers.
Split-Pane IDE
A pro-grade 3-pane IDE: Detailed Specs | Smart Editor | Simulation Console.
Instant Verification
Lightning-fast simulation with real-time pass/fail feedback and success animations.
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Progress from Trainee to Silicon Master through our comprehensive 10-level hardware curriculum.
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