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Logic Design Progress
Basic Logic Gates 0%
Combinational Logic 0%
Sequential Logic 0%
Shift Registers 0%
Finite State Machines (FSM) 0%
Counter Design 0%
Engineering Career Path
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Logic
Apprentice
Goal: 6 Solved
ââ
Junior RTL
Engineer
Goal: 15 Solved
âââ
Associate
Designer
Goal: 30 Solved
đ
Hardware
Engineer
Goal: 50 Solved
đ đ
Design
Specialist
Goal: 75 Solved
đ đ đ
Senior RTL
Engineer
Goal: 100 Solved
đ
Systems
Architect
Goal: 130 Solved
đđ
Principal
Architect
Goal: 170 Solved
đ
Implementation Lead
Goal: 220 Solved
đ
Silicon
Master
Goal: 250+ Solved