HDL2Chips IDE

0 ns/s | Tests: 0/0
FILES
design.v
testbench.v
HIERARCHY
Editor
Waveform Viewer
Schematic
No cursors
Signals / Scopes

No Waveform Trace

Run a simulation with dump.vcd generation enabled to view signal transitions in the viewer.

ADVERTISEMENT
Your Ad Here
Compiler: Connected
© 2026 HDL2Chips · Verilog IDE v2.1 Professional

Console

[00:00:00] Console initialized. Ready for simulation.